Presentation
Arrow: A Soft RISC-V Vector Accelerator for Machine Learning Inference
DescriptionIn this paper we present Arrow, a configurable hardware accelerator architecture that implements a subset of the RISC-V vector ISA extension aimed at edge machine learning inference. Our experimental results show that a soft Arrow co-processor can execute
a suite of vector and matrix benchmarks fundamental to machine learning inference 2 – 78× faster than a RISC soft processor while consuming 20% – 99% less energy when implemented in a Xilinx XC7A200T-1SBG484C FPGA.
a suite of vector and matrix benchmarks fundamental to machine learning inference 2 – 78× faster than a RISC soft processor while consuming 20% – 99% less energy when implemented in a Xilinx XC7A200T-1SBG484C FPGA.
Event Type
Work-in-Progress Poster
TimeWednesday, July 12th6:00pm - 7:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security