Presentation
A Discrete 2.5D Chiplet Library and Optimized Mapping of AI Algorithms for Heterogeneous In-memory Acceleration
DescriptionNew 2.5D chiplet-based architectures are promising to scale up the in-memory computing (IMC) system through high bandwidth network-on-package (NoP). Given an AI algorithm, the non-uniform distribution of weights and activations in each layer determines the heterogeneous configuration of IMC chiplet size and its bandwidth, respectively. We first establish a discrete chiplet library for convolutional and graph neural networks, by optimizing computing and communication energy/delay. Furthermore, we develop an end-to-end synthesis method, which maps the algorithm layer-wise to the chiplets in the library. Our approach exploits the heterogeneity in algorithms and achieves much higher energy efficiency over a homogeneous design.
Event Type
Work-in-Progress Poster
TimeTuesday, July 11th6:00pm - 7:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security