Presentation
Automated feedthrough path generation and validation flow at RTL level based on floorplan aware specification of channel-less SoC
DescriptionAs the size of the chips grows, partitioning the floor plan into manageable physical design blocks has become essential to assure the feasibility of place and route activities. This leads to new challenges in some other respects, one of which is the routing of data buses between physical partitions. For example, networking chip architecture inherently requires payload, header, and control buses to be routed across the chip. Based on the floorplan of the chip, this requires several buses to be routed over multiple physical design blocks and pipelined to meet the timing requirements. The proposed automation flow enables physical design engineers to generate RTL with the floorplan-aware routing of such buses, along with support for pipelining to meet timing requirements as well as generating metal routing rules, to perform floor plan routing activity in a fully closed loop system without external dependency. Given this floorplan-aware routing is available at the RTL level using the proposed automation, it enables functional validation at the RTL level itself instead of requiring gate level netlist.
Event Type
Work-in-Progress Poster
TimeWednesday, July 12th6:00pm - 7:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security