An Iterative Method for Mapping-Aware Frequency Regulation in Dataflow Circuits
DescriptionDataflow circuits promise to overcome the scheduling limitations of standard HLS solutions. However, their performance suffers due to timing overheads caused by the communication protocol complexity. Current pipelining solutions fail to account for logic optimizations that occur during FPGA synthesis, producing over-conservative results. In this work, we develop an FPGA mapping-aware timing regulation technique for dataflow circuits; it relies on FPGA synthesis information to identify the circuit's critical path and optimize it through register placement. Our dataflow circuits Pareto-dominate state-of-the-art solutions: while employing fewer buffers, they achieve higher operating frequencies and consistently meet the desired clock period targets.
TimeWednesday, July 12th10:55am - 11:10am PDT
Location3002, 3rd Floor
RTL/Logic Level and High-level Synthesis