Presentation
AVX Timing Side-Channel Attacks against Address Space Layout Randomization*
DescriptionModern x86 processors support an AVX instruction set to boost performance. However, this extension may cause security issues. We discovered that there are vulnerable properties in implementing masked load/store instructions. Based on this, we present a novel AVX timing side-channel attack that defeats the address space layout randomization. We demonstrate the significance of our attack by showing User/Kernel ASLR breaks on the recent Intel/AMD processors in various environments, including cloud computing, an SGX enclave, and major OSes. We further demonstrate user behavior detection. We highlight that stronger isolation or more fine-grained randomization should be adopted to successfully mitigate our attacks.
Event Type
Research Manuscript
TimeThursday, July 13th4:10pm - 4:25pm PDT
Location3003, 3rd Floor
RISC-V
Security
Hardware Security: Attack and Defense