Presentation
Accelerating Irregular Applications on Dataflow Architectures through Software and Hardware co-Design
DescriptionDataflow architectures can achieve much better performance and higher efficiency than general-purpose core. Unfortunately, dataflow architectures have so far only been effective on applications with regular compute patterns.
To this end, we first introduce a DFG balancing technique to solve load imbalance caused by irregularity. Second, we find that irregular applications have abundant pipeline parallelism within DFG nodes that can be used to boost utilization. Therefore, we decouple threads within the DFG nodes into consective pipeline stages and provide
architectural support. Experiments show that our method improves performance
by gmean 2.55× (and up to 3.71×) over a conventional dataflow architecture.
To this end, we first introduce a DFG balancing technique to solve load imbalance caused by irregularity. Second, we find that irregular applications have abundant pipeline parallelism within DFG nodes that can be used to boost utilization. Therefore, we decouple threads within the DFG nodes into consective pipeline stages and provide
architectural support. Experiments show that our method improves performance
by gmean 2.55× (and up to 3.71×) over a conventional dataflow architecture.
Event Type
Work-in-Progress Poster
TimeWednesday, July 12th6:00pm - 7:00pm PDT
LocationLevel 2 Lobby
AI
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