Presentation
Quickloop: An efficient, FPGA-accelerated exploration of parameterized RTL generators
DescriptionFPGAs are facilitating RTL simulations due to their rapid turnaround time (TAT). However, this TAT is restrictive to their use in Design Space Exploration, especially with parameterized RTL generators that unleash a gigantic full-stack search space. We propose Quickloop, an efficient framework to enable FPGA-accelerated exploration. Quickloop wraps RTL generators, software stack, and tooling into OpenAI-Gym environments with casecadability, scalability and replay. Quickloop's TAT is analytically optimized via a novel parametric and differential algorithm. Our evaluation shows that Quickloop effectively reduces episodal time to 50% as the episode approaches to realistic lengths, when compared to conventional and incremental FPGA toolflows.
Event Type
Work-in-Progress Poster
TimeTuesday, July 11th6:00pm - 7:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security