Presentation
PIM-HLS: Automatic Hardware Generation and Scheduling for Processing-in-Memory-based Neural Network Accelerators
DescriptionIn recent years, neural networks (NNs) have become a powerful tool in various fields. Processing-in-memory (PIM) architectures have become a promising resolution for NN acceleration due to their large computation capability and storage density. However, PIM architectures require manually design, which is expensive and time-consuming. In this paper, we propose PIM-HLS, an automatic hardware generation and scheduling framework for PIM-based NN accelerators. In PIM-HLS, we perform layer-wise hardware design optimization and dynamic weight scheduling for better performance under a given area constraint. Evaluation results show that PIM-HLS can achieve 10x performance improvement compared to existing PIM architectures.
Event Type
Research Manuscript
TimeWednesday, July 12th11:25am - 11:40am PDT
Location3002, 3rd Floor
EDA
RTL/Logic Level and High-level Synthesis