Presentation
HDSuper: Algorithm-Hardware Co-design for Light-weighted High-quality Super Resolution Accelerator
DescriptionAlgorithm and hardware co-design has become a great demand for the current artificial intelligence (AI) based accelerator. To improve hardware efficiency, the light-weighted algorithm should be considered. In addition, the hardware resource and utilization influence the performance of the AI accelerator. In this paper, we present a high-quality super-resolution accelerator based on the algorithm-hardware co-design technique, considering both algorithm and hardware innovations. We provide a DSSA algorithm to provide a high PSNR and SSIM neural-network-based super-resolution algorithm. Also, we design a reconfigurable hardware architecture, namely HDSuper with a uniform processing element core supporting various different computation operations.
Event Type
Research Manuscript
TimeWednesday, July 12th10:40am - 10:55am PDT
Location3006, 3rd Floor
Design
SoC, Heterogeneous, and Reconfigurable Architectures