Presentation
Sparse Hamming Graph: A Customizable Network-on-Chip Topology
SessionLet's Network with Chiplets
DescriptionChips with hundreds to thousands of cores require scalable networks-on-chip (NoCs). Customization of the NoC topology is necessary to reach the diverse design goals of different chips. We introduce sparse Hamming graph, a novel NoC topology with an adjustable cost-performance trade-off that is based on four NoC topology design principles we identified. To efficiently customize this topology, we develop a toolchain that leverages approximate floorplanning and link routing to deliver fast and accurate cost and performance predictions. We demonstrate how to use our methodology to achieve any desired cost-performance trade-off while outperforming established topologies in cost, performance, or both.
Event Type
Research Manuscript
TimeWednesday, July 12th10:40am - 10:55am PDT
Location3008, 3rd Floor
Design
Design Methodologies for System-on-Chip and 3D/2.5D System-in Package