Presentation
When Monte-Carlo Dropout Meets Multi-Exit: Optimizing Bayesian Neural Networks on FPGA
DescriptionBayesian Neural Networks (BayesNNs) have demonstrated their capability of quantifying calibrated uncertainty of their outputs, which can be used in safety-critical applications.
However, the high algorithmic complexity and poor hardware performance of BayesNNs hinder their deployment in real-life applications.
To address these challenges,
this paper proposes a novel multi-exit Monte-Carlo Dropout (MCD)-based BayesNN, which preserves high-quality uncertainty prediction with low algorithmic complexity.
To further reduce the barrier to the deployment of BayesNNs,
we propose a transformation framework that can automatically generate FPGA-based accelerators for multi-exit MCD-based BayesNN.
We intend to open-source our code and submit it for artifact evaluation.
However, the high algorithmic complexity and poor hardware performance of BayesNNs hinder their deployment in real-life applications.
To address these challenges,
this paper proposes a novel multi-exit Monte-Carlo Dropout (MCD)-based BayesNN, which preserves high-quality uncertainty prediction with low algorithmic complexity.
To further reduce the barrier to the deployment of BayesNNs,
we propose a transformation framework that can automatically generate FPGA-based accelerators for multi-exit MCD-based BayesNN.
We intend to open-source our code and submit it for artifact evaluation.
Event Type
Research Manuscript
TimeWednesday, July 12th2:25pm - 2:40pm PDT
Location3010, 3rd Floor
Design
SoC, Heterogeneous, and Reconfigurable Architectures