Presentation
STRIVE: Enabling Choke Point Detection and Timing Error Resilience in a Low-Power Tensor Processing Unit
DescriptionRapid growth in Deep Neural Network (DNN) workloads has increased the energy footprint of the Artificial Intelligence (AI) computing realm. For optimum energy efficiency, we propose operating a DNN hardware in the Low-Power Computing (LPC) region. However, operating at LPC causes increased sensitivity to Process Variation (PV). Choke point is an intriguing consequence of PV. In this paper, we demonstrate the vulnerability of DNNs to choke points, substantially lowering the prediction accuracy. To overcome choke points, we present STRIVE—a post-fabrication choke detection and reactive error reduction technique. We also introduce a time-borrow correction technique to ensure error-free DNN computation.
Event Type
Research Manuscript
TimeWednesday, July 12th1:55pm - 2:10pm PDT
Location3002, 3rd Floor
EDA
Timing and Low Power Design