Graph Representation Learning for Microarchitecture Design Space Exploration
DescriptionDesign optimization of modern microprocessors is a complex task due to the exponential growth of the design space. This work presents GRL-DSE, an automatic microarchitecture search framework based on graph embeddings. GRL-DSE uses graph representation learning to build a compact and continuous embedding space. Multi-objective Bayesian optimization design space exploration using an ensemble surrogate model proceeds directly in the graph embedding space to efficiently and holistically optimize performance-power-area (PPA) objectives. Experimental studies on RISC-V BOOM show that GRL-DSE outperforms previous techniques by 74.59\% on Pareto front quality and outperforms manual designs in terms of PPA.
Event Type
Research Manuscript
TimeWednesday, July 12th10:55am - 11:10am PDT
Location3003, 3rd Floor
AI/ML Application and Infrastructure