Presentation
Uint-Packing: A Unsigned Full-Integer DSP Packing Method Multiples Your DNN Accelerator Performance
DescriptionDSP blocks are undoubtedly efficient solutions for implementing multiply-accumulate (MAC) operations on FPGA. Since DSP resources are scarce in FPGA, the advanced solution is to pack parallel multiplication operations into a single DSP. However, available methods are based on signed-type multiplication, which leads to both the loss of accuracy and increased area.
To solve these issues simultaneously, we propose an unsigned integer generalization model called uint-packing. Guided by this generalization model, we design the novel computational structure of the DNN accelerator. Our system design is state-of-the-art, with 3.2x throughput and 3.6x energy efficiency compared to the third-place DAC-SDC'22 design.
To solve these issues simultaneously, we propose an unsigned integer generalization model called uint-packing. Guided by this generalization model, we design the novel computational structure of the DNN accelerator. Our system design is state-of-the-art, with 3.2x throughput and 3.6x energy efficiency compared to the third-place DAC-SDC'22 design.
Event Type
Research Manuscript
TimeWednesday, July 12th11:10am - 11:25am PDT
Location3012, 3rd Floor
Design
AI/ML System and Platform Design