Presentation
AMACC: Asynchronous Memory Access Accelerator for RISC-V Embedded Soft Processors
DescriptionSoft processors are widely deployed on a large scale in FPGAs to achieve massive memory parallelism and throughput. However, the low frequency and simple pipeline structures primarily adopted hinder soft processors to leverage the bandwidth provided by DDR memories, which limits their application range.
In this work, we propose an asynchronous memory access accelerator (AMACC) based on the emerging RISC-V architecture in nowadays embedded market. AMACC empowering soft processors achieve higher memory-level parallelism by providing asynchronous memory instructions and decoupled request-response logic. Evaluation shows that AMACC improved the bandwidth utilization of random access by 86% and sequential access by 5.96 times with little effect on timing, power and area through careful design, also compatible with the original cache hierarchy.
In this work, we propose an asynchronous memory access accelerator (AMACC) based on the emerging RISC-V architecture in nowadays embedded market. AMACC empowering soft processors achieve higher memory-level parallelism by providing asynchronous memory instructions and decoupled request-response logic. Evaluation shows that AMACC improved the bandwidth utilization of random access by 86% and sequential access by 5.96 times with little effect on timing, power and area through careful design, also compatible with the original cache hierarchy.
Event Type
Work-in-Progress Poster
TimeTuesday, July 11th6:00pm - 7:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security