AccALS: Accelerating Approximate Logic Synthesis by Selection of Multiple Local Approximate Changes
DescriptionApproximate computing is an energy-efficient computing paradigm for error-tolerant applications. To automatically synthesize approximate circuits, many iterative approximate logic synthesis (ALS) methods have been proposed. However, most of them do not consider applying multiple local approximate
changes (LACs) in a single round, which can lead to a much shorter runtime. In this paper, we propose AccALS, a novel framework for Accelerating iterative ALS flows, based on simultaneous selection of multiple LACs in a single round. The experimental results showed that compared to a state-of-the-art method, AccALS accelerates by up to 9.6× with a negligible circuit quality loss.
Event Type
Research Manuscript
TimeThursday, July 13th1:40pm - 1:55pm PDT
Location3002, 3rd Floor
RTL/Logic Level and High-level Synthesis