Presentation
FSPA: An FeFET-based Sparse Matrix-dense Vector Multiplication Accelerator
DescriptionSparse matrix-dense vector multiplication (SpMV) is widely used in various applications. The performance of traditional SpMV accelerators is bounded by memory. In-memory computing (IMC) is a promising technique to alleviate the memory bottleneck. The current IMC accelerator cannot support sparse storage format and in-situ floating-point multiplication at the same time. In this paper, we propose FSPA, an ferroelectric field-effect transistor (FeFET) based SpMV accelerator. FSPA integrates novel content-addressable memory (CAM) arrays and multiply-add computation (MAC) arrays to support sparse matrices represented in the floating-point format. FSPA achieves significant speedups and energy savings over CPU, GPU and two state-of-the-art IMC accelerators.
Event Type
Research Manuscript
TimeTuesday, July 11th4:10pm - 4:25pm PDT
Location3010, 3rd Floor
Design
In-memory and Near-memory Computing Circuits