DARIC: A Data Reuse-Friendly CGRA for Parallel Data Access via Elastic FIFOs
DescriptionCoarse-Grained Reconfigurable Arrays (CGRAs) are a promising architecture for data-intensive applications. For parallel data accesses, uniform memory partitioning is usually introduced to CGRA. However, uniform memory partitioning not only suffers from a local minimum, but also introduces non-negligible overhead for banking function. Therefore, we propose a data reuse-friendly CGRA (DARIC) enabling non-uniform memory partitioning. With well elaborated configurable bank groups cooperated with register chains, elastic FIFOs can be achieved. Correspondingly, a mapping algorithm supporting path sharing is proposed. Finally, the experimental results show that DARIC can achieve 2.24 X throughput and 2.58 X energy efficiency as compared to the state-of-the-art.
TimeWednesday, July 12th10:55am - 11:10am PDT
Location3006, 3rd Floor
SoC, Heterogeneous, and Reconfigurable Architectures