Presentation
Formal Verification of Restoring Dividers made Fast and Simple
DescriptionThe paper describes a formal verification method for hardware implementation of restoring divider circuits. The method is based on setting selected signals to predefined constants to reduce the design to easily verifiable circuit components, followed by their verification using equivalence checking and SAT. In contrast to previous approaches, the verification is done on a functional level without any reverse engineering of the internal structure. It facilitates debugging by localizing the source of a bug, a feature not currently available from the existing verification tools. The results show significant improvement in verification time compared to other methods.
Event Type
Research Manuscript
TimeThursday, July 13th1:55pm - 2:10pm PDT
Location3010, 3rd Floor
EDA
Design Verification and Validation