Presentation
Feedback Buffer Insertion: An Efficient Method for Pipelined Processors Design with High-Level Synthesis
DescriptionHigh-Level Synthesis (HLS) has been popularly utilized to levitate the abstraction level of the electronic system design. However, the control domain hardware, e.g., processors, is rarely designed with HLS, which hinders the possible design space exploration. To tackle this problem, we propose the Feedback Buffer Insertion (FBI) technique to assist the HLS tools in generating high-quality pipelined processor architecture from the untimed behavioral level. We demonstrate the superiority of FBI by implementing a configurable 32-bit RISC-V processor core, which excels in the area-performance Pareto frontier among other HLS-based designs and even some manually optimized RTL-base processor cores.
Event Type
Work-in-Progress Poster
TimeTuesday, July 11th6:00pm - 7:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security