Scalable Optimal Layout Synthesis for NISQ Quantum Processors
DescriptionHaving a layout synthesis tool with high solution quality is important to maximize circuit performance and fidelity for NISQ application. Previous heuristic approaches have been shown to be far from optimal. Alternatively, exact approaches are not scalable due to inefficient encodings and slow optimization methods in constraint solvers. In this paper, we propose a scalable optimal layout synthesis tool with a succinct formulation and better encoding techniques. Experimental results show that our tool can achieve 2327x speedup over the state-of-the-art exact synthesizer. Compared to the leading heuristic synthesizer, we can achieve 18x depth reduction and reduce SWAP by 62%.
Event Type
Research Manuscript
TimeTuesday, July 11th11:25am - 11:40am PDT
Location3003, 3rd Floor
Quantum Computing