Presentation
PowerPruning: Selecting Weights and Activations for Power-Efficient Neural Network Acceleration
SessionCircuit Design Potpourri
DescriptionA major challenge of deploying compute-intensive DNNs on hardware, especially on edge devices, is power consumption. We propose PowerPruning, a novel method to reduce power consumption in digital neural network accelerators by selecting weights and activations that lead to less power consumption in MAC operations. In addition, sensitized path delays of the circuits implementing MAC operations are reduced due to this weight/activation selection, which thus allows a scaling of supply voltage to reduce power consumption further. Together with retraining, the proposed method can reduce power consumption of DNNs on hardware by up to 82.1% with only a slight accuracy loss.
Event Type
Research Manuscript
TimeTuesday, July 11th10:40am - 10:55am PDT
Location3010, 3rd Floor
Design
AI/ML, Digital, and Analog Circuits