Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement
DescriptionTiming closure is crucial across the circuit design flow. Since obtaining sign-off performance needs time-consuming routing flow, all the previous early-stage timing optimization works only focus on optimizing early timing metrics. However, there is no consistency guarantee between early-stage metrics and sign-off timing performance. To enable an explicit early-stage optimization on the sign-off timing metrics, we propose a novel timing refinement framework, TSteiner. This paper demonstrates the ability of learning framework to perform robust and efficient timing optimization in the early stage through comprehensive and convincing experimental results on real-world designs.
Event Type
Research Manuscript
TimeWednesday, July 12th4:55pm - 5:10pm PDT
Location3002, 3rd Floor
Physical Design and Verification