Presentation
Automating Constraint-Aware Datapath Optimization using E-Graphs
DescriptionNumerical hardware design requires aggressive optimization, where designers exploit branch constraints, creating optimization opportunities that are valid only on a sub-domain of input space. We developed an RTL optimization tool that automatically learns the consequences of conditional branches and exploits that knowledge to enable deep optimization. The tool deploys custom built program analysis based on abstract interpretation theory, which when combined with a data-structure known as an e-graph simplifies complex reasoning about program properties. Our tool fully-automatically discovers known floating-point architectures from the computer arithmetic literature and out-performs baseline EDA tools, generating up to 33% faster and 41% smaller circuits.
Event Type
Research Manuscript
TimeWednesday, July 12th11:10am - 11:25am PDT
Location3002, 3rd Floor
EDA
RTL/Logic Level and High-level Synthesis