Codasip's Data Driven Design Methodology Part 2
DescriptionA key to innovation is rapid experimentation with rapid incorporation of what is learned. Codasip's RISCV Intellectual Property (IP) cores combined with its suite of processor development tools, Studio Configurator and Studio Designer, bring this development process into processor design. Data Driven Design (DDD) Methodology is based on experimentation and quickly making decisions based on data and not theory to optimize a processor's solution. New ideas that may take 4 to 6-weeks to implement in traditional RTL design can be quickly implemented, tested, and updated with lessons learned. Codasip's customers which have followed this process have stated that they have experimented with new design concepts in an hour which would have taken more than a month using traditional processor design flows. Codasip's tool suite enables rapid experimentation through its High Level Synthesis language (HLS), CodAL, and its integrated toolchain which can generate within minutes a compiler that utilizes your new custom instructions, transforming theory into reality. The Codasip tools include an assembler, simulator, profiler, c-libraries, c-compiler and the ability to generate RTL of your custom processor for FPGA and ASIC integration.
TimeTuesday, July 11th3:40pm - 4:00pm PDT
LocationRISC-V Zone Theater