Predictive analytics for cryogenic CMOS in future quantum computing systems
DescriptionThis presentation will cover the various challenges and their impacts on the development of next-generation quantum computing hardware. It will focus on cryo-CMOS hardware design, challenges associated with noise and mismatch for analog and mixed-signal cryo-CMOS designs, and instrumentation complexity. Specific hardware design examples will be described using 14nm CMOS technology and will cover mixed-signal hardware including memory design techniques, write channel hardware, low noise amplifiers, and interaction of CMOS with transmon qubits.
Special Session (Research)
TimeThursday, July 13th11:30am - 12:00pm PDT
Location3001, 3rd Floor