Presentation
Timing Challenges at Advanced Technology Nodes and Acceleration by Heterogeneous Programming and Machine Learning
DescriptionTiming analysis is essential to every step in the circuit design flow. Due to its high computational complexity, timing analysis has become the bottleneck of the entire design flow. Timing analysis, verifying the timing performance of a design under worst-case conditions, is of particular importance to design closure. In this tutorial, we start with timing challenges and considerations at advanced technology nodes from the foundry's perspective, followed by acceleration techniques, including heterogeneous programming and machine learning for expediting timing analysis and optimization.
Talk 1: Timing/Power/Reliability Challenges in Physical Design at Advanced Technology Nodes
Speaker: Florin Dartu or Kevin Chen (TSMC)
Abstract: Semiconductor industry has been following Moore’s Law to scale the technology to improve overall performance at reduced power and cost. However, the days of happy scaling are gone. Fabrication of chips is facing more and more difficulties thus introducing stricter DRC rules and more non-ideal process effects. For the process-induced timing, power, and reliability challenges at advanced technology nodes, we will investigate their impacts on physical design, and explore possible solutions to analysis and optimization.
Talk 2: Task-Parallel Programming System for Implementing Heterogeneous STA Algorithms
Speaker: Tsung-Wei Huang (University of Utah)
Abstract: As design complexity continues to grow exponentially, static timing analysis (STA) has quickly become the major bottleneck in the design closure flow. A key fundamental challenge is that STA tools must incorporate new parallel paradigms comprising manycore CPUs and GPUs to achieve transformational performance milestones. However, this goal is impossible to achieve without a novel computing system to assist us with the implementation complexities of parallelizing STA, such as irregular task parallelism, concurrency controls, and dynamic control flow. In this talk, we will start with a new task-parallel programming system called Taskflow to streamline the implementation complexity of heterogeneous STA algorithms. We will discuss how to formulate STA algorithms into CPU-GPU parallel tasks that accelerate both graph-based and path-based analysis workloads.
Talk 3: Machine Learning in Timing Analysis
Speaker: Iris Hui-Ru Jiang (National Taiwan University)
Abstract: STA is regarded as a crucial and essential step to achieve timing closure. As the evolution of the IC industry, the design complexity grows rapidly, and timing analysis has thus become a bottleneck due to its high computational cost. To improve the efficiency of timing analysis, machine learning techniques have been extensively applied to various timing analysis tasks recently. In this talk, we will review the recent advancements of machine learning based timing analysis techniques. For example, wire timing prediction at various design stages; predicting the timing in signal integrity (SI) mode based on the timing reported from non-SI mode; delay degradation induced by the aging effect; graph neural networks for timing macro modeling for facilitating hierarchical STA; speeding up multi-corner timing analysis in the era of corner explosion.
Talk 4: Deep Learning Enabled Timing Optimization in Physical Design
Speakers: Yibo Lin (Peking University)
Abstract: Timing closure is critical to VLSI circuit design. With continuous shrinking of technology nodes, design complexity grows dramatically with more and more complicated timing models, significantly increasing the difficulty of timing optimization. Physical design is an important stage in the design flow to achieve timing closure. It follows an iterative optimization procedure and requires repeated timing evaluation, which makes timing optimization extremely time-consuming. In this talk, we will introduce the most recent timing optimization strategies in physical design enabled by deep learning. We will discuss how deep learning enables fast timing evaluation, inspires timing differentiability, and assists timing-driven decision making. We will also explain how to accelerate timing optimization on heterogeneous computing platforms with deep learning toolkit.
Talk 1: Timing/Power/Reliability Challenges in Physical Design at Advanced Technology Nodes
Speaker: Florin Dartu or Kevin Chen (TSMC)
Abstract: Semiconductor industry has been following Moore’s Law to scale the technology to improve overall performance at reduced power and cost. However, the days of happy scaling are gone. Fabrication of chips is facing more and more difficulties thus introducing stricter DRC rules and more non-ideal process effects. For the process-induced timing, power, and reliability challenges at advanced technology nodes, we will investigate their impacts on physical design, and explore possible solutions to analysis and optimization.
Talk 2: Task-Parallel Programming System for Implementing Heterogeneous STA Algorithms
Speaker: Tsung-Wei Huang (University of Utah)
Abstract: As design complexity continues to grow exponentially, static timing analysis (STA) has quickly become the major bottleneck in the design closure flow. A key fundamental challenge is that STA tools must incorporate new parallel paradigms comprising manycore CPUs and GPUs to achieve transformational performance milestones. However, this goal is impossible to achieve without a novel computing system to assist us with the implementation complexities of parallelizing STA, such as irregular task parallelism, concurrency controls, and dynamic control flow. In this talk, we will start with a new task-parallel programming system called Taskflow to streamline the implementation complexity of heterogeneous STA algorithms. We will discuss how to formulate STA algorithms into CPU-GPU parallel tasks that accelerate both graph-based and path-based analysis workloads.
Talk 3: Machine Learning in Timing Analysis
Speaker: Iris Hui-Ru Jiang (National Taiwan University)
Abstract: STA is regarded as a crucial and essential step to achieve timing closure. As the evolution of the IC industry, the design complexity grows rapidly, and timing analysis has thus become a bottleneck due to its high computational cost. To improve the efficiency of timing analysis, machine learning techniques have been extensively applied to various timing analysis tasks recently. In this talk, we will review the recent advancements of machine learning based timing analysis techniques. For example, wire timing prediction at various design stages; predicting the timing in signal integrity (SI) mode based on the timing reported from non-SI mode; delay degradation induced by the aging effect; graph neural networks for timing macro modeling for facilitating hierarchical STA; speeding up multi-corner timing analysis in the era of corner explosion.
Talk 4: Deep Learning Enabled Timing Optimization in Physical Design
Speakers: Yibo Lin (Peking University)
Abstract: Timing closure is critical to VLSI circuit design. With continuous shrinking of technology nodes, design complexity grows dramatically with more and more complicated timing models, significantly increasing the difficulty of timing optimization. Physical design is an important stage in the design flow to achieve timing closure. It follows an iterative optimization procedure and requires repeated timing evaluation, which makes timing optimization extremely time-consuming. In this talk, we will introduce the most recent timing optimization strategies in physical design enabled by deep learning. We will discuss how deep learning enables fast timing evaluation, inspires timing differentiability, and assists timing-driven decision making. We will also explain how to accelerate timing optimization on heterogeneous computing platforms with deep learning toolkit.
Event Type
Tutorial
TimeMonday, July 10th1:30pm - 5:00pm PDT
Location3008, 3rd Floor
AI
EDA