Close
 

Presenter

Matheus Cavalcante
ETH Zürich
Presentations
Research Manuscript
Sparse Hamming Graph: A Customizable Network-on-Chip Topology
Design
Design Methodologies for System-on-Chip and 3D/2.5D System-in Package
Research Manuscript
HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement
Design
Design Methodologies for System-on-Chip and 3D/2.5D System-in Package
Research Manuscript
PATRONoC: Parallel AXI Transport Reducing Overhead for Network-on-Chips targeting Multi-Accelerator DNN Platforms at the Edge
Design
AI/ML System and Platform Design