Session
Let's Network with Chiplets
Event TypeResearch Manuscript
Design
Design Methodologies for System-on-Chip and 3D/2.5D System-in Package
TimeWednesday, July 12th10:30am - 12:00pm PDT
Location3008, 3rd Floor
DescriptionThe advent of chiplet-based SoC has revolutionized the electronics industry by enabling higher performance and increased scalability. Chiplet-based SoCs consist of multiple smaller chips, called chiplets, which are combined to form a complete system. NoC is an essential component of chiplet-based SoCs, providing high-speed communication between the chiplets and ensuring efficient data transfer. This session presents latest innovations in the realm of chiplet-based system architecture and energy-efficient NoC design. The topics covered range from the benefit of employing chiplets over monolithic design, high-performance chiplet arrangement schema, to customizable traditional NoC design, and ultra-fast optical interconnect topologies.
Presentations
10:30am - 10:40am PDT | Lightning Talk: High Fidelity Benchmarking of Interposer Material Choices Using 2.5D Design Tools | |
10:40am - 10:55am PDT | Sparse Hamming Graph: A Customizable Network-on-Chip Topology | |
10:55am - 11:10am PDT | Chiplets: How Small is too Small? | |
11:10am - 11:25am PDT | Toward Parallelism-Optimal Topology Generation for Wavelength-Routed Optical NoC Designs | |
11:25am - 11:40am PDT | HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement |