Session
This is Formal...But You Can Come Casual!
Session Chairs
Event TypeResearch Manuscript
EDA
Design Verification and Validation
TimeThursday, July 13th1:30pm - 3:00pm PDT
Location3010, 3rd Floor
DescriptionThis session covers checking and formal verification techniques. A brand new technique for sequential equivalence checking without the restriction of cycle accuracy that is elegant and performant. A new way to think of verification of dividers- functional abstractions without the memory overhead of arithmetic rewriting. An extension of basic accelerator verification to incorporate interfering actions. An end to end checking procedure for complex fully homomorphic encryption engines inspired by compiler design techniques.
Presentations
1:30pm - 1:40pm PDT | Lightning Talk: A Perspective on Formal Verification | |
1:40pm - 1:55pm PDT | SE3: Sequential Equivalence Checking for Non-cycle-accurate Design Transformations | |
1:55pm - 2:10pm PDT | Formal Verification of Restoring Dividers made Fast and Simple | |
2:10pm - 2:25pm PDT | G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators | |
2:25pm - 2:40pm PDT | Towards A Formally Verified Fully Homomorphic Encryption Compute Engine |