Close

Session

Research Manuscript: This is Formal...But You Can Come Casual!
Event TypeResearch Manuscript
Topics
EDA
Keywords
Design Verification and Validation
TimeThursday, July 13th1:30pm - 3:00pm PDT
Location3010, 3rd Floor
DescriptionThis session covers checking and formal verification techniques. A brand new technique for sequential equivalence checking without the restriction of cycle accuracy that is elegant and performant. A new way to think of verification of dividers- functional abstractions without the memory overhead of arithmetic rewriting. An extension of basic accelerator verification to incorporate interfering actions. An end to end checking procedure for complex fully homomorphic encryption engines inspired by compiler design techniques.