Research Manuscript: Progress from the Leading Edge of RTL Synthesis
Event TypeResearch Manuscript
RTL/Logic Level and High-level Synthesis
TimeThursday, July 13th1:30pm - 3:00pm PDT
Location3002, 3rd Floor
DescriptionChallenging contributions from approximate logic synthesis by means of non-conflicting multiple local approximation changes, from technology mapping based on structural choices on non-overlapping subgraphs, and from an optimization framework to design multiplier based on reinforcement learning. Last but not least, a general EDA optimization scheme based on analytic
gradient-descent without reinforcement learning: its success in the case of gate sizing opens new perspectives where reinforcement learning suffers from sample inefficiency and limited generalization.