Session
Progress from the Leading Edge of RTL Synthesis
Session Chair
Event TypeResearch Manuscript
EDA
RTL/Logic Level and High-level Synthesis
TimeThursday, July 13th1:30pm - 3:00pm PDT
Location3002, 3rd Floor
DescriptionChallenging contributions from approximate logic synthesis by means of non-conflicting multiple local approximation changes, from technology mapping based on structural choices on non-overlapping subgraphs, and from an optimization framework to design multiplier based on reinforcement learning. Last but not least, a general EDA optimization scheme based on analytic
gradient-descent without reinforcement learning: its success in the case of gate sizing opens new perspectives where reinforcement learning suffers from sample inefficiency and limited generalization.
gradient-descent without reinforcement learning: its success in the case of gate sizing opens new perspectives where reinforcement learning suffers from sample inefficiency and limited generalization.
Presentations
| 1:30pm - 1:40pm PDT | Lightning Talk: Latest Trends in Industrial Logic Synthesis | |
| 1:40pm - 1:55pm PDT | AccALS: Accelerating Approximate Logic Synthesis by Selection of Multiple Local Approximate Changes | |
| 1:55pm - 2:10pm PDT | Lightweight Structural Choices Operator for Technology Mapping | |
| 2:10pm - 2:25pm PDT | AGD: A Learning-based Optimization Framework for EDA and its Application to Gate Sizing | |
| 2:25pm - 2:40pm PDT | RL-MUL: Multiplier Design Optimization with Deep Reinforcement Learning |