Session
Route Me if You Can!
Event TypeResearch Manuscript
EDA
Physical Design and Verification
TimeTuesday, July 11th3:30pm - 5:30pm PDT
Location3008, 3rd Floor
DescriptionWe journey through advances in routing algorithms spanning PCB, chiplet, and ASIC. First, we visit PCB routing with a highly efficient algorithm handling multiple design rules and algorithms for solving the escape and bus routing problems. Next, we meet a novel algorithm that solves the any-angle multi-redistribution routing problem for chiplets. Then, a highly efficient directed acyclic graph-based routing algorithm will be introduced. The fifth work takes a fresh look at solving the routing problem via an ILP Lagrangian relaxation and a direction-aware A* algorithm. The final work presents OpenDRC, a GPU-accelerated design rule checker.
Presentations
| 3:30pm - 3:40pm PDT | Lightning Talk: Feasibility Checking for Advanced Packaging | |
| 3:40pm - 3:55pm PDT | A Matching Based Escape Routing Algorithm with Variable Design Rules and Constraints | |
| 3:55pm - 4:10pm PDT | Disjoint-Path and Golden-Pin Based Irregular PCB Routing with Complex Constraints | |
| 4:10pm - 4:25pm PDT | Any-Angle Routing for Redistribution Layers in 2.5D IC Packages | |
| 4:25pm - 4:40pm PDT | EDGE: Efficient DAG-based Global Routing Engine | |
| 4:40pm - 4:55pm PDT | Pathfinding Model and Lagrangian-Based Global Routing | |
| 4:55pm - 5:10pm PDT | OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration |
