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Session

Research Manuscript: New Discoveries in Classical Hardware Security Problems
Session Chairs
Reza Azarderakhsh
Florida Atlantic University
Ning Zhang
Washington University, St. Louis
Event TypeResearch Manuscript
Topics
RISC-V
Security
Keywords
Hardware Security: Primitives, Architecture, Design & Test
TimeTuesday, July 11th10:30am - 12:00pm PDT
Location3012, 3rd Floor
DescriptionClassical problems last with new meanings and applications. This session has four papers on three classical hardware security problems: IP protection, side-channel analysis, and hardware true random number generator. The first paper reports a new obfuscation mechanism to establish trust with low overhead. ActiWate presented in the second paper is a new watermark-based SoC IP protection that can be verified by system peripherals. Authors in the third paper discover a new problem in SPICE simulation for side-channel analysis. The last paper shows a novel architecture to generate true random numbers by ring oscillators with high throughput and energy efficiency.
Presentations
10:30am - 10:40am PDTLightning Talk - The Incredible Shrinking Black Box Model
Author
Patrick Schaumont
10:40am - 10:55am PDTHybrid Obfuscation of Chiplet-Based Systems
Authors
Yousef Safari
Pooya Aghanoury
Subramanian Iyer
Nader Sehatbakhsh
Boris Vaisband
10:55am - 11:10am PDTActiWate: Adaptive and Design-agnostic Active Watermarking for IP Ownership in Modern SoCs
Authors
Zahin Ibnat
Mohammad Rahman
Mridha Md Mashahedur Rahman
Hadi Mardani Kamali
Mark Tehranipoor
Farimah Farahmandi
11:10am - 11:25am PDTOn the unpredictability of SPICE simulations for Side-channel Leakage Verification of Masked Cryptographic Circuits
Authors
Kazuki Monta
Makoto Nagata
Josep Balasch
Ingrid Verbauwhede
11:25am - 11:40am PDTAn Ultra High-Throughput and Energy-Efficient TRNG Exploiting Four FPGA-Compatible Ring Oscillators and One Multiphase Sampler
Authors
Zhaojun Lu
Houjia Qidiao
Qidong Chen
Zhenglin Liu
Jiliang Zhang