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Session

Back-End Design: Hot Hot Chips: Ensuring Stable Power Delivery of an SoC System
Session Chair
Lakshmanan Balasubramanian
Texas Instruments (India) Pvt. Ltd.
IEEE
Event TypeBack-End Design
Topics
Back-End Design
TimeMonday, July 10th10:30am - 12:00pm PDT
Location2008, Level 2
DescriptionPower Delivery and Thermal Management are now foundations to make a Hot Chip look cool in its working. Gather around the fire to learn stories from the adventures of fellow travelers.
Presentations
10:30am - 10:45am PDTIR-Drop Aware Power Layout Optimization Methodology for Full-Custom Design
Presenter
Seonghyeon Park
10:45am - 11:00am PDTAutomated MIMCAP insertion solution for Turn-Around-Time Reduction
Presenters
Ingeol Lee
Kiwon Yoon
Jongho Kim
Jun Seomun
Sangyun Kim
11:00am - 11:15am PDTThermal Aware On-Die Electrical Analysis
Presenter
Anubhav Johri
11:15am - 11:30am PDTHigh Bandwidth Memory (HBM3-7.2Gbps) 2.5D-IC Integration with Signal Interconnects and Power Distributed Networks Design-Optimization
Presenters
Sam Yang
Joseph Wang
Ethan Lin
Justin Hsieh
11:30am - 11:45am PDTCANCELED - Thermal aware Vectorless EM/IR signoff for High Speed Custom Digital IPs
Presenter
Ayan Roy Chowdhury
11:45am - 12:00pm PDTSystem Power Integrity Analysis: from the PMIC to the Transistor
Presenter
Shane Stelmach