Session

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Front-End Design: Adapting to a New Era in Front-End Design and Verification of Power

Session Chair

Homayoon Akhiani

NVIDIA

Event TypeFront-End Design

Topics

TimeMonday, July 10th3:30pm - 5:00pm PDT

Location2010, 2nd Floor

DescriptionPower management is a fundamental component in the electrical components used every day. Whether it’s the latest smart phones, vehicle electrification, or the global appetite for more data centers, effective power management is critical to availability, reliability, and cost reduction. In this session, you will gain insight into techniques to optimize power during the front-end design stages: including the latest on power analysis techniques and methodologies leveraging real world case studies.

Presentations

3:30pm - 3:45pm PDT	Node Based Clock Gating: Reducing NoC Power in Low Bandwidth Scenario Presenters Kyurae Lee Wooil Kim
3:45pm - 4:00pm PDT	Low Power and Area Efficient 64 Bit Vedic Multiplier Design for High Speed Operation in ASIC-DSP Applications. Presenters Pooja Krishnamurthy Priyanka Gharat Sastry Puranapanda Darshan Sarode
4:00pm - 4:15pm PDT	Power Intent Automation for Ultra Low Power Mixed-Signal SoC Presenters Sai Sudarsan Chitrapu Ruchi Shankar Ankitha M Penchal Kumar Gajula Lakshmanan Balasubramanian Gaurav Kumar
4:15pm - 4:30pm PDT	Low power DAC sub-system for Digital Beam Forming Chip Presenters Ankur Bal Rupesh Singh
4:30pm - 4:45pm PDT	Full SoC power analysis and estimation with end-user software early in the design cycle Presenters Jongwoo Ryu Jinsuk Youn Woojoo Kim Kunhyuk Kang Amir Attarha Justin Lee BK Yoon
4:45pm - 5:00pm PDT	Unique metric driven vector qualification and Ranking for peak power coverage Presenters Seunghyeon Park Jinsuk Youn Wojoo Kim Kunhyuk Kang