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Session

IP: Implementation Aspects for Leading-Edge IP
Session Chair
Shankar Hemmady
Blue Horizons
Event TypeIP
Topics
IP
TimeTuesday, July 11th1:30pm - 3:00pm PDT
Location2012, 2nd Floor
DescriptionIP vendors provide verified IP. During digital and analog implementation, the rubber hits the road. This session will discuss key implementation aspects, including DFT for memories in automotive, weak link detection in memory periphery, SoC sign-off aspects, layout closure turn-around-time, noise analysis, and automation of the creation of chiplet interfaces across technology nodes.
Presentations
1:30pm - 1:45pm PDTAdvanced DFT method using Checker and Indication FFs on Automotive NAND Flash Memory
Presenters
Yong Lee
Joon Kim
Seokjun Jang
Sungho Kang
1:45pm - 2:00pm PDTWeak Link Detection in Memory Periphery using Design Robustness Analysis
Presenters
Ashish Kumar
Shashank Gupta
Rakesh Shenoy
Rayson Yam
Rohit Kumar Gupta
2:00pm - 2:15pm PDTThe Art of Breaking Things Down - Hierarchical Abstraction for Power Sensitive SoC Signoff
Presenters
Gaurav Pratap
Sachin Bansal
Nupur Gupta
Chirag Patel
Vishal Keswani
Amit Goldie
2:15pm - 2:30pm PDTReduced Layout Closure TAT and Compute Resources by Accelerating DRC Signoff Analysis through an Incremental Approach
Presenters
Shobhit Kumar Garg
Samichi Shrivastava
Koby Zand
Rajesh Karturi
2:30pm - 2:45pm PDTFast and Accurate Phase Noise Analysis of Crystal Oscillator in 28 FDSOI Process
Presenters
Sahil Kumar
Nitin Jain
Atul Bhargava
Prayes Jain
2:45pm - 3:00pm PDTAutomatic Chiplet Interface IP Generation Across Technology Nodes, Vendors, and Stacks Using Intelligent IP
Presenters
Benjamin Prautsch
Andy Heinig