Session

DescriptionPackaging in the new era of Moore's Law will offer extreme levels of die integration/bonding and begin to blur the boundary between on- and off-chip connectivity (especially in 3D architectures) due to ever denser physical I/O interfaces/bonds. This new form of ‘packaging' is often referred to as ‘Heterogeneous Integration' or HI today. A common goal for HI is to enable the interconnection of multiple dice (or "chiplets”) of various functionalities in a manner that approaches monolithic-like performance yet utilizes advanced off-chip interconnects and packaging/assembly to provide flexibility in IC fabrication and design, improved scalability, reduced development time, and reduced cost. In fact, a cost-benefit analysis of monolithic die disaggregation was recently performed at the 3 nm node and showed that chiplets become cost competitive when monolithic die size exceeds 150 mm2 due to yield considerations of larger monolithic die [1].

The aim of this session is look at emerging technologies and extreme HI architectures that seek to eliminate the boundaries between on-chip and off-chip connectivity.

[1] K. Kim, "The smallest engine transforming humanity: the past, present, and future,” in Proc. IEEE
International Electron Devices Meeting (IEDM), 2021