Session

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Engineering Track Poster: Wednesday Engineering Track Poster Reception

Event TypeEngineering Track Poster

Topics

TimeWednesday, July 12th5:00pm - 6:00pm PDT

LocationLevel 2 Exhibit Hall

Presentations

5:00pm - 5:01pm PDT	3D IC Inter-Die Test Implementation Using IEEE1838 Authors Keunsoo Lee Kunhyuk Kang Joon Kim Vistrita Tyagi
5:01pm - 5:03pm PDT	3DIC Design floorplanning flow and Early Area Estimation for Area optimization Authors Yongjin Hong Jongho Kim Jun Seomun Sangyun Kim
5:03pm - 5:04pm PDT	A Data Analytics Based Approach for Reducing Clock Tree Power at RTL Authors Manish Kumar Vishnu Kanwar Vishal Kashyap Gaurav Garkoti Mohammed Fahad Divya Bareja Bhupesh Prajapat Vijay Tayal Amit Dey
5:04pm - 5:06pm PDT	A Machine Learning Approach Towards SKILL Code Autocompletion Author Enrique Dehaerne
5:06pm - 5:07pm PDT	A Novel Hierarchical Power Integrity Signoff Methodology for Ultra Large SoCs Authors Rossana Liu Medha Kulkarni Pranav Ranganathan Piyush Jain Rushin Patel Ajit Gokhale Lucas Chaves
5:07pm - 5:09pm PDT	Accelerating Datapath Verification using Formal techniques Authors Bhavya Sri Dasari Jaaneshwaran A Craig Deaton Uday Kumar Karthik Rajakumar
5:09pm - 5:10pm PDT	Advanced Node PPA and Design Optimization Using Cerebrus ML Flow Authors Rahul Mandal Balamurugan Sekar Kiran Kumar Samuel Di Pietro
5:10pm - 5:12pm PDT	An Accurate System Level Transient Voltage Droop Analysis Methodology for High Performance GPGPU Power Delivery Network Authors Yuanyuan Ling Ling Sun Tieqing Chen Zhenhua Gan Shixuan Que Shuqiang Zhang Xiaoxia Zhou
5:12pm - 5:13pm PDT	An Efficient and Spice Aligned Method for Complex IO's Behavioral Model Generation and Verification Authors natish Singla SAURABH SRIVASTAVA Harsh Garg Avinav Joshi Matthieu Fillaud Atul Bhargava Anil Dwivedi
5:13pm - 5:15pm PDT	An efficient methodology to verify floating point matrix multiplication Authors Nicolae Tusinschi Gerardo Nahum Sasa Stamenkovic
5:15pm - 5:16pm PDT	Automated Analog Model Generation for High Quality Verification using Event Driven Simulators Authors Aadhar Sharma Lakshmanan Balasubramanian Saurabh Pandey Aastha Nitesh Dave Mayank Mehta Jaeha Kim
5:16pm - 5:18pm PDT	Automatic Generation of 22FDX® OpAmp Designs in the Virtuoso® Suite by Incorporating ID-Xplore™ for Sizing with IIP Layout Generators Authors Benjamin Prautsch Ramy Iskander
5:18pm - 5:19pm PDT	Automated and integrated Dynamic Voltage Drop IR-ECO flow on Automotive ADAS SoCs Authors Manish Kumar Govind Pal Samant Paul Anil Yadav Atul Bhargava Amit Jangra Koshy John
5:19pm - 5:21pm PDT	Bridging IR Drop and Timing Analysis Signoff for Execution Excellence in Graphics Designs Author Srim Karthik Kanneganti
5:21pm - 5:23pm PDT	Challenges and custom methodology involved in successful physical implementation of C-Shaped / Wrapped DDRPHY IP solution Authors Sachin Revannavar Saiprasad Gollapinni Pushpanjali Pinnu Roshan Kumar Gangadhar Naik Greg ford
5:23pm - 5:24pm PDT	Chiplet Design and Verification using an Open Standard Markup Language Authors James Wong Jawad Nasrullah
5:24pm - 5:26pm PDT	Clustering of Assertions using ML/AI in Formal Verification Authors Viraj Rawal S R Pavitra Vishwajith Rao
5:26pm - 5:27pm PDT	Efficient methodologies for STL certification of Spinoff SOC designs. Authors Arif Mohammed Chandra Has Dondapati Sanjay Singh Vishal Bhadauria Subham Mohapatra Prasanth Viswanathan Pillai Krishna Allam
5:27pm - 5:29pm PDT	Electrical Analysis using Hierarchical Approach On Ultra Large Designs Authors Sainarayanan Karatholuvu Suryanarayanan Rakesh Thadimarri Reddy
5:29pm - 5:30pm PDT	EM/IR Signoff Methodology for Large size Mixed Signal Custom Blocks in High Speed IOs Authors Ayan Roy Chowdhury Richa Agrawal
5:30pm - 5:32pm PDT	FORMAL VERIFICATION CONTRACT BASED SoC SECURITY VALIDATION Authors Kiran Rampurkar Ketan Baladaniya Harshal Mumbaikar Manoj Kumar Munigala surinder sood
5:32pm - 5:33pm PDT	Hazard Detection Tool in Asynchronous Finite State Machines Transition Logic Authors Roberta Priolo Francesco Battini Enea Dimroci
5:33pm - 5:35pm PDT	High-Performance Design with Rapid RTL Profiling of Critical Power Scenarios Authors Alexander Pivovarov Vidhu Joshi Mehdi Sadi
5:35pm - 5:36pm PDT	HW Security Path Validation Using Formal Methods: Intel Case Studies Authors Alex Levin Sayak Ray
5:36pm - 5:38pm PDT	Improving Design Robustness by Accounting for Device Skew in Static Timing Analysis Authors Aftab Khan Wenwen Chai ayhan mutlu Li Ding
5:38pm - 5:39pm PDT	Integration of Intel Thermal Model with Design-for-Reliability Flow Authors Lei Jiang Daniel Pantuso Prabhakar Marepalli Colin Landon Mohammed Shahid Sanjay Murthy Mike Wang
5:39pm - 5:41pm PDT	Intent Based Timing Constraints Authors Hemlata Gupta Adil Bhanji Manish Verma Jennifer Basile Kerim Kalafala Jack DiLullo
5:41pm - 5:43pm PDT	IO Designs for reliability in advanced technology nodes Authors Manoj Kumar Kailash Kumar Akhil Thotli Prateek Singh Nitin Bansal
5:43pm - 5:44pm PDT	Leveraging Integrated Silicon Photonics for a Streamlined GPU Architecture Authors Luca Ramini Jinsung Youn Marco Fiorentino Steven Dean Raymond Beausoleil
5:44pm - 5:46pm PDT	Novel CAD Methodology for IR Drop and Reliability Verification of Stacked Dies (3D-IC) Authors Matthew Jastrzebski Roger Hayward Noel Pereira
5:46pm - 5:47pm PDT	Novel Chip-Package-System thermal analysis with RTL Power Authors Chenyang Zhang Zhongming Hou Chen Lin shuqiang zhang Bin Guo
5:47pm - 5:49pm PDT	Novel Hierarchical IREM Sign-off Flow using ROM Authors Dongyoun Yi Seonghun Jeong Byunghyun Lee
5:49pm - 5:50pm PDT	Overcoming Challenges in Functional Verification of Automotive Traffic Schedulers Authors Harshit Jaiswal Hemlata Bist
5:50pm - 5:52pm PDT	Reuse of Lint Waivers: An Approach to Relay Knowledge & Guide Synthesis Authors Amit Goldie Himanshu Kathuria Suresh Barla Vrinda Padmakumari Rohit Kumar Ohlayan Paras Mal Jain Lokesh Ahuja
5:52pm - 5:53pm PDT	RV (Reliability Verification) Automation To Improve Execution Efficiency Authors Raj Dua Brahmaiah Throvagunta Narendra Kumar Bhuma, Jaya Priyanka Bhagwat Sandeep Dappili
5:53pm - 5:55pm PDT	SigmaDVD (sDVD): High Coverage Solution for Power Integrity Signoff Authors Anusha Vemuri Emmanuel Chao Santosh Santosh Chidambaram Rakkappan Ed Deeters
5:55pm - 5:56pm PDT	Special Bit Pattern Injection in Simulation Verification by leveraging Formal Verification Authors Viraj Rawal Vishwajith Rao Nivin George
5:56pm - 5:58pm PDT	Static Analysis for Early Detection and Efficient Debug Authors Hormoz Yaghutiel Guru Shindaghatta Kanad Chakraborty
5:58pm - 5:59pm PDT	CANCELED - Tips & Facts That Every Design Engineer Should Know About RTL Synthesis Author Clifford Cummings