Engineering Track Poster: Wednesday Engineering Track Poster Reception
Event TypeEngineering Track Poster
Back-End Design
Embedded Systems
Front-End Design
TimeWednesday, July 12th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
5:00pm - 5:01pm PDT3D IC Inter-Die Test Implementation Using IEEE1838
5:01pm - 5:03pm PDT3DIC Design floorplanning flow and Early Area Estimation for Area optimization
5:03pm - 5:04pm PDTA Data Analytics Based Approach for Reducing Clock Tree Power at RTL
5:04pm - 5:06pm PDTA Machine Learning Approach Towards SKILL Code Autocompletion
5:06pm - 5:07pm PDTA Novel Hierarchical Power Integrity Signoff Methodology for Ultra Large SoCs
5:07pm - 5:09pm PDTAccelerating Datapath Verification using Formal techniques
5:09pm - 5:10pm PDTAdvanced Node PPA and Design Optimization Using Cerebrus ML Flow
5:10pm - 5:12pm PDTAn Accurate System Level Transient Voltage Droop Analysis Methodology for High Performance GPGPU Power Delivery Network
5:12pm - 5:13pm PDTAn Efficient and Spice Aligned Method for Complex IO's Behavioral Model Generation and Verification
5:13pm - 5:15pm PDTAn efficient methodology to verify floating point matrix multiplication
5:15pm - 5:16pm PDTAutomated Analog Model Generation for High Quality Verification using Event Driven Simulators
5:16pm - 5:18pm PDTAutomatic Generation of 22FDX® OpAmp Designs in the Virtuoso® Suite by Incorporating ID-Xplore™ for Sizing with IIP Layout Generators
5:18pm - 5:19pm PDTAutomated and integrated Dynamic Voltage Drop IR-ECO flow on Automotive ADAS SoCs
5:19pm - 5:21pm PDTBridging IR Drop and Timing Analysis Signoff for Execution Excellence in Graphics Designs
5:21pm - 5:23pm PDTChallenges and custom methodology involved in successful physical implementation of C-Shaped / Wrapped DDRPHY IP solution
5:23pm - 5:24pm PDTChiplet Design and Verification using an Open Standard Markup Language
5:24pm - 5:26pm PDTClustering of Assertions using ML/AI in Formal Verification
5:26pm - 5:27pm PDTEfficient methodologies for STL certification of Spinoff SOC designs.
5:27pm - 5:29pm PDTElectrical Analysis using Hierarchical Approach On Ultra Large Designs
5:29pm - 5:30pm PDTEM/IR Signoff Methodology for Large size Mixed Signal Custom Blocks in High Speed IOs
5:32pm - 5:33pm PDTHazard Detection Tool in Asynchronous Finite State Machines Transition Logic
5:33pm - 5:35pm PDTHigh-Performance Design with Rapid RTL Profiling of Critical Power Scenarios
5:35pm - 5:36pm PDTHW Security Path Validation Using Formal Methods: Intel Case Studies
5:36pm - 5:38pm PDTImproving Design Robustness by Accounting for Device Skew in Static Timing Analysis
5:38pm - 5:39pm PDTIntegration of Intel Thermal Model with Design-for-Reliability Flow
5:39pm - 5:41pm PDTIntent Based Timing Constraints
5:41pm - 5:43pm PDTIO Designs for reliability in advanced technology nodes
5:43pm - 5:44pm PDTLeveraging Integrated Silicon Photonics for a Streamlined GPU Architecture
5:44pm - 5:46pm PDTNovel CAD Methodology for IR Drop and Reliability Verification of Stacked Dies (3D-IC)
5:46pm - 5:47pm PDTNovel Chip-Package-System thermal analysis with RTL Power
5:47pm - 5:49pm PDTNovel Hierarchical IREM Sign-off Flow using ROM
5:49pm - 5:50pm PDTOvercoming Challenges in Functional Verification of Automotive Traffic Schedulers
5:50pm - 5:52pm PDTReuse of Lint Waivers: An Approach to Relay Knowledge & Guide Synthesis
5:52pm - 5:53pm PDTRV (Reliability Verification) Automation To Improve Execution Efficiency
5:53pm - 5:55pm PDTSigmaDVD (sDVD): High Coverage Solution for Power Integrity Signoff
5:55pm - 5:56pm PDTSpecial Bit Pattern Injection in Simulation Verification by leveraging Formal Verification
5:56pm - 5:58pm PDTStatic Analysis for Early Detection and Efficient Debug
5:58pm - 5:59pm PDTCANCELED - Tips & Facts That Every Design Engineer Should Know About RTL Synthesis