BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20230712T175214Z
LOCATION:3008\, 3rd Floor
DTSTART;TZID=America/Los_Angeles:20230712T162500
DTEND;TZID=America/Los_Angeles:20230712T164000
UID:dac_DAC 2023_sess148_RESEARCH730@linklings.com
SUMMARY:SPET: Transparent SRAM Allocation and Model Partitioning for Real-
 time DNN Tasks on Edge TPU
DESCRIPTION:Research Manuscript\n\nChanghun Han (Ajou University), Hoon Su
 ng Chwa (Daegu Gyeongbuk Institute of Science and Technology), Kilho Lee (
 Soongsil University), and Sangeun Oh (Ajou University)\n\nDeep neural netw
 orks (DNNs) have recently been deployed in many real-time safety-critical 
 embedded systems. To support DNN tasks in real-time, most previous studies
  focused on GPU or CPU. However, Edge TPU has not yet been studied for rea
 l-time guarantee. This paper presents real-time DNNs framework for Edge TP
 U environments that satisfy multiple DNN inference tasks' timing requireme
 nts. This framework provides 1) SRAM allocation and model partitioning tec
 hniques, and 2) MIP-based algorithm that determines amounts of SRAM and se
 gment count for each task. The experiment result shows that our framework 
 provides 37% higher schedulability than the existing Edge TPU system.\n\nT
 opic: Embedded Systems\n\nKeyword: Time-Critical System Design\n\nSession 
 Chairs: Fanxin Kong (Syracuse University) and Song Han (University of Conn
 ecticut)
END:VEVENT
END:VCALENDAR
