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DTSTAMP:20230712T175214Z
LOCATION:2008\, Level 2
DTSTART;TZID=America/Los_Angeles:20230712T153000
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UID:dac_DAC 2023_sess185_BED101@linklings.com
SUMMARY:Accelerated design convergence using automatic recipe tuning throu
 gh Intel enabled AI-ML PnR framework
DESCRIPTION:Back-End Design\n\nRohit Kumar, Raghavendra Vasappanavara, Jag
 adeesh Boddu, and Narendra Nimmagadda (Intel)\n\nAs we enter Armstrong Era
  of fabrication, how innovatively we can converge complex designs with fas
 ter TAT and best-in-class PPA & QoR is becoming significant. Manual design
  convergence efforts for finding best PPA convergence recipes are time con
 suming and tedious. This is due to manual design explorations and analysis
  done across multiple RTL2GDS runs, trying out various experiments to find
  out best recipes. This can sometime be error-prone or non-optimal solutio
 n as well. The problem is exacerbated for early designs where collaterals 
 for full PnR runs are not stable and adds to challenge of navigating throu
 gh collaterals stability issues while finding out best recipes. We are pro
 posing Intel enabled AI-ML PnR framework which helps designers find out be
 st PPA convergence recipe in automated and timebound manner. Takes designe
 r guard bands as input other than regular design collaterals and ensures r
 ecommended recipe meets general design requirements. Further, the AI-ML re
 cipe recommender can be sliced only for PnR flow stages (Place, Clock or r
 oute recipes) where usable collaterals are available in early design stage
 s to help designers quickly converge on early design netlist. This helps i
 n improved feedback loop and faster design maturity other than convergence
 .\n\nTopic: Back-End Design\n\nSession Chair: Michael Kazda (IBM)
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