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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20230712T175212Z
LOCATION:2010\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20230711T133000
DTEND;TZID=America/Los_Angeles:20230711T134500
UID:dac_DAC 2023_sess188_FED113@linklings.com
SUMMARY:An automated flow for High Performance Asynchronous Digital Contro
 llers
DESCRIPTION:Front-End Design\n\nEnea Dimroci, Roberta Priolo, and Francesc
 o Battini (STMicroelectronics)\n\nDigital asynchronous logic design is a t
 echnique used to reach high performance in digital controllers for some an
 alog IPs. The asynchronous digital controller is usually a local IP put in
 side the analog IP to minimize delays, power consumptions, area and boost 
 the whole system performance.\n\nThis flow generates RTL code, timing cons
 traints and regioning scripts for submodules (input logic, handshake logic
  and output logic) of the asynchronous digital controller.\nIn particular,
  the regioning applied during the implementation phase is the key point to
  meet the timing requirements for these kind of applications.\nAlso, a spe
 cific Static Timing Analysis for asynchronous digital controllers has been
  defined to guarantee that the timing constraints are met.\n\nThe use of t
 his flow allows designers to reduce design time through automation. The re
 sults have shown an improvement on timing performance around 5%-10% with r
 espect to the results obtained without regioning constraints.\n\nThis appr
 oach has been successfully applied to a large number of designs, resulting
  in a significant reduction in design time and effort to meet the required
  performance.\n\nTopic: Front-End Design\n\nSession Chair: Vikas Sachdeva 
 (Real Intent Inc)
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