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DTSTAMP:20230712T175159Z
LOCATION:2010\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20230711T103000
DTEND;TZID=America/Los_Angeles:20230711T120000
UID:dac_DAC 2023_sess191_FED126@linklings.com
SUMMARY:Design for Verification - Case Reopened
DESCRIPTION:Front-End Design\n\nNicola Nicolici (McMaster University), Dav
 id Akselrod (AMD), Sankaran Menon (Intel), Badri Gopalan (Synopsys), Pouya
  Taatizadeh (Google), and Steve Sunter (Siemens EDA)\n\nThere is a need to
  evolve the verification methodologies of complex system-on-a-chip (SoC) d
 evices and add new dimensions to the mindsets employed across different st
 ages of verification. A major complexity is now added to the SoC design an
 d SoC verification challenges by industry's adopting chiplet-based SoC des
 ign. Design for Verification (DfV) is a natural evolution in both design a
 nd verification methodologies. The central idea of DfV is that specialized
  hardware blocks can be leveraged across different stages of design verifi
 cation (IP block, SoC, emulation, silicon prototype) not only to address t
 he transfer of verification test plans/data between different environments
  (e.g., pre-silicon vs emulation vs post-silicon) but also to make the ver
 ification more effective and efficient at each of these verification stage
 s. While different aspects of DfV have been employed across multiple proje
 cts in different organizations (possibly even unknowingly on some occasion
 s), it is important to bring different stakeholders together to share thou
 ghts and improve the collective understanding of DfV and articulate its lo
 ng-term benefits.\n\nTopic: Front-End Design\n\nSession Chair: David Aksel
 rod (AMD)
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