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DTSTAMP:20230712T175211Z
LOCATION:2012\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20230710T134500
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UID:dac_DAC 2023_sess202_IP115@linklings.com
SUMMARY:Improved Peak Power Interval Detection using the Sliding Window Po
 wer Profile (SWPP)
DESCRIPTION:IP\n\nSaebit Jeong (Samsung Electronics); Manish Kumar (Siemen
 s EDA); Kunhyuk Kang, Woojoo Kim, and Jinsuk Youn (Samsung Electronics); a
 nd Vishnu Kanwar, Vishal Kashyap, BK Yoon, and Minsub Byun (Siemens EDA)\n
 \nIn this work, we address the challenge of accurately identifying peak po
 wer intervals in the modern SOC design process. The intervals are simulati
 on periods of high-power demand that can impact performance and may lead t
 o chip failure. Existing Interval Based Power Profile (IBPP) methods can b
 e insufficient (up to 50% average power of the interval) for correctly ide
 ntifying these high average power consuming intervals due to various reaso
 ns described in this proposal. To address this issue, jointly with Samsung
 , we propose a methodology using the Simple Moving Average (SMA) technique
  to create a Sliding Window Peak Power Profile (SWPP). Our results demonst
 rate that the SWPP can accurately identify the correct intervals with the 
 highest power consumption, as compared to existing IBPP methods. We apply 
 the SWPP method to a case study involving real Samsung projects and demons
 trate its effectiveness compared to existing IBPP methods. Our results sug
 gest that the SWPP is a simple yet effective approach that can be applied 
 to a wide range of other low-power design projects. Jointly developed with
  Samsung, this method has the potential to improve decision-making in the 
 low-power design process.\n\nTopic: IP, RISC-V\n\nSession Chair: Vidyasaga
 r Ganesan (AMD)
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