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X-LIC-LOCATION:America/Los_Angeles
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TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
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TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
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BEGIN:VEVENT
DTSTAMP:20230712T175211Z
LOCATION:2012\, 2nd Floor
DTSTART;TZID=America/Los_Angeles:20230710T161500
DTEND;TZID=America/Los_Angeles:20230710T163000
UID:dac_DAC 2023_sess203_IP117@linklings.com
SUMMARY:A Robust Framework for High Speed Link Verification with a Profici
 ent Way to Close the Functional Coverage
DESCRIPTION:IP\n\nPiyush Tankwal, Arnab Ghosh, Piyush Agnihotri, Mukesh Ga
 ndhi, and Parag S. Lonkar (Samsung R&D (SSIR))\n\nThe motive of the propos
 ed work is to discuss a general verification framework which reduces the e
 ffort and time taken in High-Speed Link DV activity while maintaining the 
 quality. Simulation time can be reduced to a great extent by introducing s
 ave-and-restore mechanism which cuts down the repeated simulation activity
  like link initialization and training. In complex Link design like UniPro
 , there are many functional coverage bins and it is very hard to cover tha
 t many bins with random regression given the time constraint. A smart cove
 rage closure technique is discussed involving test ranking and Perl script
  integration for quick turnaround. The script extracts the statistics of u
 n-hit bins and creates a directed test suite to hit those specific bins wi
 th a single run. Also, to find bug at the initial stage of verification so
 me scenarios are proposed which create simulation condition close to the r
 eal world by incorporating skew and lane mapping.\n\nTopic: IP
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