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DTSTAMP:20230712T175159Z
LOCATION:DAC Pavilion\, Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20230711T140000
DTEND;TZID=America/Los_Angeles:20230711T144500
UID:dac_DAC 2023_sess238_PAVP103@linklings.com
SUMMARY:Design Considerations and Tradeoffs for 2.5D Chiplet Solutions
DESCRIPTION:DAC Pavilion Panel\n\nEd Sperling (Semiconductor Engineering),
  Saif Alam (Movellus), Craig Bishop (Deca Technologies), Mark Kuemerle (Ma
 rvell), and Tony Mastroianni (Siemens EDA)\n\nThe interest in chiplets has
  increased dramatically to expand performance, mitigate rising mask costs,
  and enable resuse. Initially, chiplets, 2.5D, and 3D solutions were reser
 ved for the knighted few, Intel with its Foveros technology, AMD's CCD for
  its Zen CPU line, and Broadcom with its Spectrum-4. Now, mid- and small-c
 ap companies alike are targeting chiplets for economic and performance rea
 sons. This panel will examine and discuss product decisions, such as die-t
 o-die interface technology, packaging considerations, and verification met
 hodologies through EDA, hyperscaler, clocking, and packaging lens.\nBefore
  entering the panel discussion, the moderator will provide the audience wi
 th a brief history of 2.5D and D2D solutions while defining key terms to p
 rovide level grounding for the audience. The panel will discuss:\n\n•     
    What factors are driving 2.5D adoption? How is this adoption changing y
 our segment?\n•        What tools, flow, methodology, and architectural co
 nsiderations are required for modern 2.5D designs?\n•        What are the 
 tradeoffs for system designers to consider when comparing BoW vs. UCIe vs.
  other solutions? What applications best suited for each technology?\n\nTh
 e panel will end with forward-looking statements on the future of 2.5D and
  3D solutions. The panelists will explore possible improvements in methodo
 logy, tools, and technology.\n\nTopic: Design
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