BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20230712T175213Z
LOCATION:Level 2 Lobby
DTSTART;TZID=America/Los_Angeles:20230711T180000
DTEND;TZID=America/Los_Angeles:20230711T190000
UID:dac_DAC 2023_sess242_RESEARCH464@linklings.com
SUMMARY:FlexNAS: Flexible Hardware Aware Training-Less Neural Architecture
  Search for FPGAs
DESCRIPTION:Work-in-Progress Poster\n\nChengdi Cao, Lorenzo Ferretti, Suha
 il Basalama, and Jason Cong (University of California, Los Angeles)\n\nCon
 current NAS and DSE of neural architectures play a fundamental role in AI 
 democratization. However, the length and cost of NAS and DSE processes, re
 quiring hundreds of GPU and CPU hours, is a limiting factor to the adoptio
 n of automated design flows.\nWe present FlexNAS, a hardware aware trainin
 g-less NAS framework for FPGAs targeting the NASBench201 space. FlexNAS ca
 n explore ~2 million implementations achieving up to 89.18%, 63.79%, 42.79
 % accuracy for the CIFAR-10, CIFAR-100 and ImageNet16-120 benchmarks while
  targeting Alveo, Kintex7, and Virtex7 FPGA families in less than 4.5 hour
 s of search time with a 0.5ms target inference latency.\n\nTopic: AI, Auto
 nomous Systems, Cloud, Design, EDA, Embedded Systems, RISC-V, Security
END:VEVENT
END:VCALENDAR