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DTSTAMP:20230712T175211Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20230710T170000
DTEND;TZID=America/Los_Angeles:20230710T180000
UID:dac_DAC 2023_sess244_ETPOST106@linklings.com
SUMMARY:Aggressor Aware Design for Better IRdrop Results
DESCRIPTION:Engineering Track Poster\n\nVlad Berlin and Eddie Reizin (Rety
 m) and Boris Shapiro (Ansys)\n\nThe move to advanced technodes has many be
 nefits, but it has created a challenge that has been previously neglectabl
 e; the aggression of neighboring cells that are linked through the power g
 rid – this link through the grid is known as cross-impedance. The complex 
 grid structure that designed with pillars create cross-impedance that stre
 tch beyond cells that share same track.\n\nTraditionally the focus of IRdr
 op analyses was mainly 2 aspects: i) improving self-drop –optimizing the c
 ell's resistive path from its power pins to the bumps. ii) handling simult
 aneous switching cells that share a power\ground track.\n\nTo improve turn
 -around-time and reduce IRdrop related ECO cycles, we can tackle the probl
 em from its origin – we can leverage Ansys Redhawk-SC platform to gather a
 nd calculate the aggression impact radius for all the cells in the library
 . The gathered data can be transformed to custom placement rules that will
  maximize cell usage while reducing overall dynamic IRdrop.\n\nAt later ma
 ture design stages, we can utilize Ansys Redhawk-SC platform to combine ag
 gressor cells in the design with their slack to a small and effective list
  of ECO's that will have most overall design IRdrop improvements while hav
 ing minimal impact on timing due to slack margin.\n\nTopic: Back-End Desig
 n, Embedded Systems, Front-End Design, IP, RISC-V
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