BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20230712T175212Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20230710T170000
DTEND;TZID=America/Los_Angeles:20230710T180000
UID:dac_DAC 2023_sess244_ETPOST108@linklings.com
SUMMARY:Power Integrity analysis of 3D stacking Structure in CMOS Image Se
 nsor Chip
DESCRIPTION:Engineering Track Poster\n\nEric Chen (Omnivision) and Xiaodon
 g Wang and Li Yahui (Ansys)\n\nFor the CMOS image sensor chip, to maximize
  the photoelectric signal conversion rate, minimize the loss, and reserve 
 more design area for more complex image processing algorithm logic , two c
 hips stacking is the common structure.  One of ASIC die is below as image 
 processing logic. The other CIS die is stacking above as Backside Illumina
 te Sensor for the perception of photoelectric signal. These two dies using
  different processes, are connected by intermediate hybrid-bonding layers.
   It makes difficulty to analyze the IR voltage drop of the PG network run
 ning through CIS die above and ASIC die below. \nWith the application of A
 nsys Redhawk-SC , which has powerful mutli-physics field co-simulation sol
 utions, it is able to investigate the coupling between two different dies 
 and multi-physics such as electric, thermal , structures etc., so as to ac
 hieve a higher simulation precision and guide designers to optimize index 
 of SI/PI/themal/reliability of structure from SoC to system.\n\nTopic: Bac
 k-End Design, Embedded Systems, Front-End Design, IP, RISC-V
END:VEVENT
END:VCALENDAR