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DTSTAMP:20230712T175211Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20230710T170000
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UID:dac_DAC 2023_sess244_ETPOST132@linklings.com
SUMMARY:A Comprehensive Thermal Solution in Advanced Large Scale 3DIC Desi
 gn
DESCRIPTION:Engineering Track Poster\n\nKeqing Ouyang, Ping Ding, Junjie C
 hen, Guohua Zhou, and Haodong Lei (Sanechips Technology Co.,Ltd) and Li Zo
 u and Chang Zhao (Ansys)\n\nThe pursuit of high integration and high perfo
 rmance 3DIC design makes the number of cells per unit area of the chip inc
 rease and thermal coupling between cell is intensified. Meanwhile, with na
 rrow 3-D fin structure and lower thermal conductivity in substrate, local 
 FinFET device temperature is higher compared to planar MOS structure. In a
 ddition, the joule heat between wires in limited space becomes severe.\n  
     Narrower physical wires, higher current density, increasing impact of 
 wire temperature on EM limit, all these factors can lead to rise of the ch
 ip temperature and worsen the electromigration(EM) phenomenon, such as ope
 n or short. To avoid function failure caused by reliability-related proble
 ms, designer restricts the design excessively with whole die set to a valu
 e higher than the maximum operating temperature in traditional flow, which
  causes difficulty to iterate and even failure to sign-off. So the accurat
 e "Thermal aware EM sign-off" is a must for advanced 3DIC design.\n    Dif
 ferent from the traditional flow, our flow can model the realistic heat di
 ssipation environment of the complicated 3DIC accurately, and meanwhile ta
 ke the thermal coupling of the instance, and the wire-to-wire joule heat i
 nto account to analyze the thermal convergence process precisely. For diff
 erent layers and locations, different temperatures (Tj) are generated. The
  realistic spatial tempatrue distribution scenario generated by system-lev
 el thermal analysis can replace the coarse global temperature setting in t
 raditional EM analysis flow.\n    With the thermal-aware EM flow, we can a
 void over-design and under-design. And the simulation results can be used 
 to provide guidance for the heat dissipation design of the system.\n\nkeyw
 ords : thermal-aware, EM-analysis, boudary condiction, system-level\n\nTop
 ic: Back-End Design, Embedded Systems, Front-End Design, IP, RISC-V
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