Presentation
Accelerated design convergence using automatic recipe tuning through Intel enabled AI-ML PnR framework
DescriptionAs we enter Armstrong Era of fabrication, how innovatively we can converge complex designs with faster TAT and best-in-class PPA & QoR is becoming significant. Manual design convergence efforts for finding best PPA convergence recipes are time consuming and tedious. This is due to manual design explorations and analysis done across multiple RTL2GDS runs, trying out various experiments to find out best recipes. This can sometime be error-prone or non-optimal solution as well. The problem is exacerbated for early designs where collaterals for full PnR runs are not stable and adds to challenge of navigating through collaterals stability issues while finding out best recipes. We are proposing Intel enabled AI-ML PnR framework which helps designers find out best PPA convergence recipe in automated and timebound manner. Takes designer guard bands as input other than regular design collaterals and ensures recommended recipe meets general design requirements. Further, the AI-ML recipe recommender can be sliced only for PnR flow stages (Place, Clock or route recipes) where usable collaterals are available in early design stages to help designers quickly converge on early design netlist. This helps in improved feedback loop and faster design maturity other than convergence.
Event Type
Back-End Design
TimeWednesday, July 12th3:30pm - 3:45pm PDT
Location2008, Level 2
Back-End Design